Non-volatile memory (“NVM”) cells are fabricated in a large variety of structures, including but not limited to Poly-silicon floating gate, as shown in FIG. 2A, and Nitride Read Only Memory (“NROM”), as shown in FIG. 2B. As is well known, an NVM cell's state may be defined and determined by its threshold voltage, the gate to source voltage at which the cell begins to significantly conduct current.
Different threshold voltage ranges are associated with different logical states, and a NVM cell's threshold voltage level may be correlated to the amount of charge (e.g. electrons) stored in a charge storage region of the cell. FIG. 1A shows a voltage distribution graph depicting possible threshold voltage distributions of a binary non-volatile memory cell, wherein vertical lines depict boundary voltage values correlated with each of the cell's possible states. Cells having Vt Lower than EV level are said to be erased verified. Cells having Vt Higher than PV are said to be program verified. These two limits define the completion of programming and erase sequences that may be performed on a cell. A Program sequence of programming pulses may be used to drive the Vt of a cell higher than PV, while an erase sequence may drive the cell's Vt lower than EV. Also visible in FIG. 1A are vertical lines designating a Read Verify (RV) level and an Intermediate Program Verify voltage, PVI, designating the start of regions before the Program Verify threshold.
FIG. 1B shows a voltage distribution graph depicting possible threshold voltage distributions in the charge storage region of a multi-level non-volatile memory cell (“MLC”), wherein one set of vertical lines depict boundary values correlated with each of the cell's possible Program Verify Threshold Voltages (PV00, PV01, etc.), another set of vertical lines depict boundary values correlated with the Read Verify level of each of the cell's possible Program states (RV00, RV01, etc.), and yet another set depict boundary lines for Intermediate Program Verify voltages (PVI00, PVI01, etc.) associated with each of the states.
The amount of charge stored in a charge storage region of an NVM cell, may be increased by applying one or more programming pulses to the cell. While the amount of charge in the cell may decrease by applying an erase pulse to the NVM cell which may force the charge reduction in the cell's charge storage region, and consequently may decrease the NVM's threshold voltage.
A simple method used for operating NVM cells (e.g. programming, reading, and erasing) uses one or more reference structures such as reference cells to generate the reference levels (i.e. PVs, EVs). Each of the one or more reference structures may be compared against a memory cell being operated in order to determine a condition or state of the memory cell being operated. Generally, in order to determine whether an NVM cell is at a specific state, for example erased, programmed, or programmed at one of multiple possible program states within a multi-level cell (“MLC”), the cell's threshold level is compared to that of a reference structure whose threshold level is preset and known to be at a voltage level associated with the specific state being tested for. Comparing the threshold voltage of an NVM cell to that of a reference cell is often accomplished using a sense amplifier. Various techniques for comparing an NVM's threshold voltage against those of one or more reference cells, in order to determine the state(s) of the NVM's cells, are well known.
When programming an NVM cell to a desired state, a reference cell with a threshold voltage set at a voltage level defined as a “program verify” level for the given state may be compared to the threshold voltage of the cell being programmed in order to determine whether a charge storage area or region of the cell being programmed has been sufficiently charged so as to be considered “programmed” at the desired state. If after a programming pulse has been applied to a cell, it has been determined that a cell has not been sufficiently charged in order for its threshold voltage to be at or above a “program verify” level (i.e. the threshold voltage of the relevant reference cell) associated with the target program state, the cell is typically hit with another programming pulse to try to inject more charge into its charge storage region. Once a cell's threshold value reaches or exceeds the “program verify” level to which it is being programmed, no further programming pulse should be applied to the cell.
Groups of cells within an NVM array may be programmed concurrently. The group of NVM cells may consist of cells being programmed to the same logical state, or may consist of cells being programmed to several possible states, such as may be the case with MLC arrays. Since not all cells have the same susceptibility to being programmed, cells may not program at the same rate. Some cells may reach a target program state before other cells in the same set of cells that are being programmed together.
The need to increase NVM's performance dictates more aggressive programming algorithm using stronger programming pulses. The stronger pulses may cause the Vt of the NVM cell to change significantly hence increasing the variations in the response of the different cells to the programming algorithm. This is reflected in the programming tail that may become larger using more aggressive algorithms. Larger Programming tails may not be wanted since they reduce the endurance and retention figures of an NVM cell.
With MLC arrays the situation is finer. The voltage threshold boundaries which define a given logical state in an MLC cell (e.g. between two read levels) are usually considerably smaller than those for a binary NVM cell. FIG. 1B, to which reference is now made, illustrates four regions of an MLC, where each region is associated with one of the programmed states of the MLC. Because in an MLC a fixed range of potential threshold voltages (e.g. 3 Volts to 9 Volts) needs to be split into several sub-ranges or regions, the size of each sub-range or region in an MLC is usually smaller than a region of a binary NVM cell, as seen comparing FIG. 1A to 1B. Programming algorithms for MLC arrays may take into account that a programming tail should not exceed the read verify reference level above it.
The simple solution of reducing the steps of a programming algorithm to smaller and smaller steps does not assure the similar reduction of the PGM tail voltage distribution. This is due to practical limitations of array non uniformities in many parameters (e.g. physical dimensions, resistances of current paths, number of cells that need programming pulses simultaneously, etc. . . . ). Since cells are programmed in groups, the applied voltages experiences by each cell may different to some extent from the pulse voltage as supplied by power supplies.
There is a need in the field of semiconductors for improved systems, circuits and methods for the programming of NVM cells in a NVM array that has more control of the PGM rates hence the variations in the programming tail.
Algorithms for programming MLC cells are known. U.S. patent application Ser. No. 10/354,050, filed on Jan. 30, 2003, assigned to the same assignee as the present invention, teaches several programming algorithms for MLC memory arrays. The specification of U.S. patent application Ser. No. 10/354,050, is hereby incorporated by reference in its entirety into the present application.